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1 fn6755.1 isl12057 low cost and low power i 2 c rtc real time clock/calendar low power and low co st rtc with alarm function and dual irq pins the isl12057 device is a low-power, real-time clock that is pin compatible and functionally equivalent to maxim ds1337 with clock/calendar and alarm function. the oscillator uses an external, low-cost 32.768khz crystal with 6pf load capacitance. th e real-time clock tracks time with separate registers for hour s, minutes, and seconds. the device has calendar registers for date, month, year, and day of the week. the calendar is accurate through 2099, with automatic leap year correction. pinouts isl12057 (8 ld soic, msop) top view isl12057 (8 ld tdfn) top view features ? pin compatible to maxim ds1337 ? functionally equival ent to maxim ds1337 ? real-time clock/calendar - tracks time in hours, minutes, and seconds - day of the week, date, month, and year ? dual interrupts for frequency output and alarm interrupts ? four selectable frequency outputs ? two alarms - settable to the second, minute, hour, day of the week, and date ?i 2 c interface - 400khz data transfer rate ? small package options - 8 ld 2mmx2mm tdfn - 8 ld msop - 8 ld soic - pb-free (rohs compliant) applications ? utility meters ? hvac equipment ? audio/video components ? set-top box/television ?modems ? network routers, hubs, switches, bridges ? cellular infrastr ucture equipment ? fixed broadband wireless equipment ? pagers/pda ? point of sale equipment ? test meters/fixtures ? office automation (copiers, fax) ? home appliances ? computer products ? other industrial/medical/automotive x1 x2 irq2 gnd 1 2 3 4 8 7 6 5 v dd irq1 /f out scl sda 2 3 4 1 7 6 5 8 x1 x2 irq2 gnd v dd irq1 /f out scl sda data sheet march 3, 2011 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2009, 2011. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
2 fn6755.1 march 3, 2011 block diagram ordering information part number part marking v dd range (v) temp. range (c) package (pb-free) pkg. dwg. # isl12057ibz (notes 1, 2) 12057 ibz 1.4 to 3.6 -40 to +85 8 ld soic m8.15 isl12057iuz (notes 1, 2) 12057 1.4 to 3.6 -40 to +85 8 ld msop m8.118 ISL12057IRUZ-T (notes 3, 4) 057 1.4 to 3.6 -40 to +85 8 ld tdfn (tape and reel) l8.2x2 isl12057evalz evaluation board notes: 1. these intersil pb-free plastic packaged pr oducts employ special pb-free material sets , molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std- 020. 2. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 3. these intersil pb-free plastic packaged pr oducts employ special pb-free material se ts; molding compounds/die attach materials and nipdau plate - e4 termination finish, wh ich is rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 4. please refer to tb347 for details on reel specifications. i 2 c interface rtc control logic alarm2 frequency out rtc divider sda buffer crystal oscillator por scl buffer sda scl x1 x2 v dd internal supply seconds minutes hours day of week date month year control registers alarm1 irq2 irq1 /f out isl12057
3 fn6755.1 march 3, 2011 pin descriptions pin number symbol description 1 x1 the x1 pin is the input of an inverting amplifier and is intended to be connected to one pin of an external 32.768khz quartz crystal. the required crystal load capacitance is 6pf. this pin can also be driven by an external 32.768khz osc illator with x2 pin floating. 2 x2 the x2 pin is the output of an inverting amplifier and is intended to be connected to one pin of an external 32.768khz quartz crystal. the required crystal load capacitance is 6pf. 3irq2 interrupt output 2 is a multi-functional pin that can be used as an alarm interrupt. this pin is open drain and requires an external pull-up resistor. this pi n is at high impedance at power-up. 4 gnd ground 5 sda serial data (sda) is a bi directional pin used to transfer serial data into and out of the device. it has an open drain outp ut and may be wire or?ed with other open drain or open collector outputs. 6 scl the serial clock (scl) input is used to cl ock all serial data into and out of the device. 7irq1 /f out interrupt output 1/frequency output is a multi-functional pin that can be used as an alarm interrupt or frequency output pin. the function is set via the configur ation register. this pin is open drain and requires an external pull-up resistor. it has a default output of 32.768khz at power-up. 8v dd power supply isl12057
4 fn6755.1 march 3, 2011 absolute maximum rati ngs thermal information voltage on v dd (respect to gnd) . . . . . . . . . . . . . . . . . -0.2v to 4v voltage on irq1 /f out , irq2 , scl and sda (respect to gnd). . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.2v to 6v voltage on x1 and x2 pins (respect to gnd). . . . . . . . . -0.2v to 4v esd rating ((per mil-std-883 method 3014) human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>4kv machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>350v thermal resistance (typical) (note 5) ja (c/w) 8 lead soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 8 lead msop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 8 lead tdfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 5. ja is measured with the component mounted on a high effective t hermal conductivity test board in free air. see tech brief tb379 for details. dc operating characteristics ? rtc temperature = -40c to +85c, unless otherw ise stated. crystal load capacitance = 6pf. boldface limits apply over the operating temperature range, -40c to +85c. symbol parameter conditions min (note 8) typ (note 7) max (note 8) units notes v dd full operation power supply 1.8 3.6 v v ddt timekeeping power supply 1.4 1.8 v i dd1 standby supply current v dd = 3.6v 600 950 na 6, 11 v dd = 3.3v 500 na i dd2 timekeeping current v dd = 1.8v 400 650 na 6, 11 v dd = 1.6v 350 na i dd3 supply current with i 2 c active at clock speed of 400khz v dd = 3.6v 15 40 a 6 i li input leakage current on scl -100 100 na i lo i/o leakage current on sda -100 100 na irq1 /f out and irq2 v ol output low voltage v dd = 1.8v, i ol = 3ma 0.4 v serial interface specifications over the recommended operating conditions unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +85c. symbol parameter test conditions min (note 8) typ (note 7) max (note 8) units notes serial interface specs v il sda and scl input buffer low voltage -0.3 0.3 x v dd v v ih sda and scl input buffer high voltage 0.7 x v dd 5.5 v hysteresis sda and scl input buffer hysteresis 0.04 x v dd v v pullup maximum pull-up voltage on sda during i 2 c communication v dd + 2 v10 v ol sda output buffer low voltage, sinking 3ma v dd > 1.8v, v pullup = 5.0v 00.4 v cpin sda and scl pin capacitance t a = +25c, f = 1mhz, v dd = 5v, v in =0v, v out = 0v 10 pf 9 f scl scl frequency 400 khz t in pulse width suppression time at sda and scl inputs any pulse narrower than the max spec is suppressed. 50 ns isl12057
5 fn6755.1 march 3, 2011 t aa scl falling edge to sda output data valid scl falling edge crossing 30% of v dd , until sda exits the 30% to 70% of v dd window. 900 ns 10 t buf time the bus must be free before the start of a new transmission sda crossing 70% of v dd during a stop condition, to sda crossing 70% of v dd during the following start condition 1300 ns t low clock low time measured at the 30% of v dd crossing 1300 ns t high clock high time measured at the 70% of v dd crossing 600 ns t su:sta start condition setup time scl rising edge to sda falling edge. both crossing 70% of v dd 600 ns t hd:sta start condition hold time from sda falling edge crossing 30% of v dd to scl falling edge crossing 70% of v dd 600 ns t su:dat input data setup time from sda exiting the 30% to 70% of v dd window, to scl rising edge crossing 30% of v dd 100 ns t hd:dat input data hold time from scl falling edge crossing 30% of v dd to sda entering the 30% to 70% of v dd window 0 900 ns t su:sto stop condition setup time from scl rising edge crossing 70% of v dd , to sda rising edge crossing 30% of v dd 600 ns t hd:sto stop condition hold time from sda rising edge to scl falling edge. both crossing 70% of v dd 600 ns t dh output data hold time from scl falling edge crossing 30% of v dd , until sda enters the 30% to 70% of v dd window 0 ns t r sda and scl rise time from 30% to 70% of v dd 20 + 0.1 x cb 300 ns 9 t f sda and scl fall time from 70% to 30% of v dd 20 + 0.1 x cb 300 ns 9, 10 cb capacitive loading of sda or scl total on-chip and off-chip 10 400 pf 9 rpu sda and scl bus pull-up resistor off-chip maximum is determined by t r and t f for cb = 400pf, max is about 2k to~2.5k . for cb = 40pf, max is about 15k to ~20k 1 k 9 notes: 6. irq1 /f out inactive. 7. typical values are for t = +25c and 3.3v supply voltage. 8. compliance to datasheet limits is assured by one or mo re methods: production test, ch aracterization and/or design. 9. these are i 2 c specific parameters and are not production tested; however, they are used to set conditions fo r testing devices to validate specification. 10. parts will work with sda pull-up voltage above the v pullup limit but the t aa and t f in the i 2 c parameters are not guaranteed. 11. specified at +25c. serial interface specifications over the recommended operating conditions unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +85c. (continued) symbol parameter test conditions min (note 8) typ (note 7) max (note 8) units notes isl12057
6 fn6755.1 march 3, 2011 sda vs scl timing symbol table t su:sto t dh t high t su:sta t hd:sta t hd:dat t su:dat scl sda (input timing) sda (output timing) t f t low t buf t aa t r waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don?t care: changes allowed changing: state not known n/a center line is high impedance figure 1. standard output load for testing the device with v dd = 5.0v sda, irq1 /f out and irq2 1533 100pf 5.0v for v ol = 0.4v and i ol = 3ma equivalent ac outp ut load circuit for v dd = 5v isl12057
7 fn6755.1 march 3, 2011 general description the isl12057 device is a low-power, real-time clock with clock/calendar, power-fail indicator, and alarm function. the oscillator uses an external, low-cost 32.768khz crystal with 6pf load capacitance. th e real-time clock tracks time with separate registers for hour s, minutes, and seconds. the device has calendar registers for date, month, year, and day of the week. the calendar is accurate through 2099, with automatic leap year correction. the isl12057 has two flexible alarms, and each can be set to any clock/calendar value for a match; for example, every minute, every tuesday, or at 5:23 a.m. on the first day of every month. the alarm status is ava ilable by checking the status register, or the device can be configured to provide a hardware interrupt via the irq1 /f out or irq2 pin. there is a repeat mode for the alarm, which allows a periodic interrupt every second or every minute. pin description x1, x2 the x1 and x2 pins are the input and output, respectively, of an inverting amplifier. an external 32.768khz quartz crystal with 6pf load capacitance is used with the isl12057 to supply a timebase for the real-time clock. see figure 6. the device can also be driven directly from a 32.768khz square wave source with peak-to-peak voltage from 0v to vdd at x1 pin with x2 pin floating. typical performance curves temperature is +25c unless otherwise specified figure 2. i dd1 vs v dd figure 3. i dd1 vs temperature figure 4. i dd vs v dd vs f out figure 5. f out vs v dd with a typical 32.768khz crystal 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 1.41.92.42.93.4 v dd (v) i dd1 (a) 0.2 0.4 0.6 0.8 1.0 -40 -20 0 20 40 60 80 temperature (c) 3.0 1.8 1.4 3.6 i dd1 (a) 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.41.92.42.93.4 i dd (a) 8192hz 1hz 32768hz 4096hz v dd (v) 32767.0 32767.2 32767.4 32767.6 32767.8 32768.0 32768.2 32768.4 32768.6 32768.8 32769.0 1.4 1.9 2.4 2.9 3.4 f out (hz) v dd (v) figure 6. recommended crystal connection x1 x2 isl12057
8 fn6755.1 march 3, 2011 irq1 /f out (interrupt output 1/frequency output) this dual-function pin can be us ed as an alarm interrupt or a frequency output pin. the irq1 /f out mode is selected via the control register (address 0eh). the irq1 /f out is an open drain output. this pin has a default output of 32.768khz at power-up. ? interrupt mode. the pin provides an interrupt signal output. this signal notifies a host processor that an alarm has occurred and requests action. ? frequency output mode. the pin outputs a clock signal that is related to the crystal frequency. the frequency output is user selectable and is enabled via the i 2 c bus. irq2 (interrupt output 2) the irq2 pin is used as an alarm1 interrupt and/or an alarm2 interru pt. the irq2 mode is selected via the control register (address 0eh). the irq2 is an open drain output. this pin is high impedance at power-up. the pin provides an interrupt signal output. this signal notifies a host processor that an alarm has occurred and requests action. serial clock (scl) the scl input is used to clock all serial data into and out of the device. the input buffer on this pin is always active (not gated). the scl pin can accept a logic high voltage up to 5.5v. serial data (sda) sda is a bi-directional pin used to transfer data into and out of the device. it has an open drain output and may be ored with other open drain or open co llector outputs. the input buffer is always active (not gated) in normal mode. an open drain output requires the use of a pull-up resistor, and it can accept a pull-up voltage up to 5.5v. the output circuitry controls the fall time of the output signal with the use of a slope-controlled pull-down. the circuit is designed for 400khz i 2 c interface speeds. note: parts will work with sda pull-up voltage above the v pullup limit, but the t aa and t f in the i 2 c parameters are not guaranteed. v dd , gnd these are chip power supply and ground pins. the device will have full operation with a power supply from 1.8v to 3.6vdc, and a timekeeping func tion with a power supply from 1.4v to 1.8v. a 0.1f decoupling capacitor is recommended on the v dd pin to ground. functional description real time clock operation the real time clock (rtc) uses an external 32.768khz quartz crystal to maintain an accurate internal representation of second, minute, hour, day of week, date, mont h, and year. the rtc also has leap-year correction. the rtc corrects for months having fewer than 31 days and has a bit that controls 24-hour or am/pm format. the clock begins incrementing after power-up with valid oscillator condition. accuracy of the real time clock the accuracy of the real time clock depends on the frequency of the quartz crystal that is used as the time base for the rtc. since the resonant frequency of a crystal is temperature dependent, rtc performance also depends upon temperature. the frequency deviation of the crystal is a function of the turnover temper ature of the crystal from the crystal?s nominal frequency. for example, a ~20ppm frequency deviation translates into an accuracy of ~1 minute per month. these parameters ar e available from the crystal manufacturer. i 2 c serial interface the isl12057 has an i 2 c serial bus interface that provides access to the real-time clock registers, the control and status registers, and the alarm registers. the i 2 c serial interface is compatible with other industry i 2 c serial bus protocols using a bi-directional data signal (sda) and a clock signal (scl). register descriptions the registers are accessible following a slave byte of ?1101000x? and they read or wr ite to addresses [00h:0fh]. the defined addresses and default values are described in table 1. register access the contents of the registers can be modified by performing a byte or a page write operati on directly to any register address. the address will wrap around from 0fh to 00h. the registers are divided into three sections: 1. real time clock (7 bytes): address 00h to 06h 2. alarm (7 bytes): address 07h to 0dh 3. control and status (2 bytes): address 0eh to 0fh there are no addresses above 0fh. a register can be read by performing a random read at any address at any time. this returns the contents of that register location. additional registers are read by performing a sequential read. for the rtc regi sters, the read instruction latches all clock registers into a buffer, so an update of the clock does not change the time being read. a sequential read will not result in the out put of data from the memory array. at the end of a read, the master supplies a stop condition to end the operation and free the bus. after a read or write instruction, the addr ess remains at the previous address plus one, so the user can execute a current address read and continue readi ng the next register. isl12057
9 fn6755.1 march 3, 2011 real-time clock registers addresses [00h to 06h] rtc registers (sc, mn, hr, dw, dt, mo, yr) these registers depict bcd repr esentations of the time. as such, sc (seconds, address 00h) and mn (minutes, address 01h) range from 0 to 59, hr (hour, address 02h) can either be a 12-hour or 24-hour mode, dw (day of the week, address 03h) is 1 to 7, dt (date, address 04h) is 1 to 31, mo (month, address 05h) is 1 to 12, and yr (year, address 06h) is 0 to 99. the dw register provides a day of the week status and uses three bits (dw2 to dw0) to represent the seven days of the week. the counter advances in the cycle, 1-2-3-4-5-6-7-1-2-? the assignment of a numerical value to a specific day of the week is arbitrary and ma y be decided by the system software designer. 24-hour time if the mil bit of the hr register is ?0?, the rtc uses a 24-hour format, and bit 5 of the hr register is the second 10-hour bit (20?23 hours). if the mil bit is ?1?, the rtc uses a 12-hour format and bit 5 of the hr register is the am /pm bit, with logic high being pm. the clock defaults to 24-hour format time. century indicator the century bit (bit 7 of the mo register) is toggled when the years register overflows from 99 to 00 to indicate the change of century. leap years leap years add the day february 29 and are defined as those years that are divisible by 4. y ears divisible by 100 are not leap years, unless they are also divi sible by 400. this means that the year 2000 is a leap year, and the year 2100 is not. the isl12057 does not correct for the leap year in the year 2100. addresses [0eh to 0fh] the control and status registers consist of the status register, interrupt, and alarm register. table 1. register memory map addr section reg name bit reg 76 5 43210rangedefault 00 h rtc sc 0 sc22 sc21 sc20 sc13 sc12 sc11 sc10 0-59 00h 01 h mn 0 mn22 mn21 mn20 mn13 mn12 mn11 mn10 0-59 00h 02 h hr 0 mil am /pm hr20 hr13 hr12 hr11 hr10 1-12 +am/pm 00h hr21 0-23 03 h dw 0 0 0 0 0 dw12 dw11 dw10 1-7 01h 04 h dt 0 0 dt21 dt20 dt13 dt12 dt11 dt10 1-31 01h 05 h mo c entur y 0 0 mo20 mo13 mo12 mo11 mo10 0-12 +century 01h 06h yr yr23 yr22 yr21 yr20 yr13 yr12 yr11 yr10 0-99 00h 07h alarm1 a1sc a1m1 a1sc22 a1sc21 a1sc20 a1sc13 a1sc12 a1sc11 a1sc10 0-59 00h 08h a1mn a1m2 a1mn22 a1mn21 a1mn20 a1mn13 a1mn12 a1mn11 a1mn10 0-59 00h 09h a1hr a1m3 a1mil a1am /pm a1hr20 a1hr13 a1hr12 a1hr11 a1hr10 1-12 +am/pm 00h a1hr21 0-23 0ah a1dw/ dt a1m4 a1dw/dt 0 0 0 a1dw12 a1dw11 a1dw10 1-7 00h a1dt21 a1dt20 a1dt13 a1dt12 a1dt11 a1dt10 1-31 00h 0bh alarm2 a2mn a2m2 a2mn22 a2mn21 a2mn20 a2mn13 a2mn12 a2mn11 a2mn10 0-59 00h 0ch a2hr a2m3 a2mil a2am /pm a2hr20 a2hr13 a2hr12 a2hr11 a2hr10 1-12 +am/pm 00h a2hr21 0-23 0dh a2dw/ dt a2m4 a2dw/dt 0 0 0 a2dw12 a2dw11 a2dw10 1-7 00h a2dt21 a2dt20 a2dt13 a2dt12 a2dt11 a2dt10 1-31 00h 0eh control int eosc 0 0 rs2 rs1 intcn a2ie a1ie n/a 18h 0fh status sr osf 0 0 0 0 0 a2f a1f n/a 80h isl12057
10 fn6755.1 march 3, 2011 interrupt control register (int) [address 0eh] oscillator enable bit (eosc ) the eosc bit enables the crystal oscillator function when it is set to ?0?. when the eosc bit is set to ?1?, the crystal oscillator function is disabled, and the device enters power- saving mode. the eosc bit is set to ?0? at power-up. frequency out control bits (rs2, rs1) these bits select the ou tput frequency at the irq1 /f out pin. intcn must be set to ?0 ? for frequency output at the irq1 /f out pin. see table 3 for frequency selection of the f out pin. interrupt control bi t (intcn) and alarm interrupt enable bits (a2ie, a1ie) the intcn bit controls the relationship between the alarm interrupts and the irq1 /f out and irq2 pins. the a2ie and a1ie bits enable the alarm interrupts, a2f and a1f, to assert the irq1 /f out and irq2 pins. see table 4 for alarm interrupt selection with intc n, a2ie and a1ie bits. status register (sr) [address 0fh] the status register is located in the memory map at address 0fh. this is a volatile re gister that provides status of oscillator failure and alarm interrupts. alarm1 interrupt bit (a1f) these bits announce if the alarm1 matches the real-time clock. if there is a match, the re spective bit is set to ?1?. this bit is manually reset to ?0? by the user. a write to this bit in the sr can only set it to ?0?, not to ?1?. alarm2 interrupt bit (a2f) these bits announce if the alarm2 matches the real-time clock. if there is a match, the re spective bit is set to ?1?. this bit is manually reset to ?0? by the user. a write to this bit in the sr can only set it to ?0?, not to ?1?. oscillator failure bit (osf) this bit is set to a ?1? when there is no oscillation on the x1 pin. the bit is set by hardware (isl12057 internally) and can only be disabled by having an oscillation on x1 and manually resetting to ?0? to reset it. alarm1 registers addresses [address 07h to 0ah] the alarm1 register bytes are set up identically to the rtc register bytes, except that the msb of each byte functions as an enable bit (enable = ?0?). these enable bits specify which alarm registers (seconds, minutes, etc.) are used to make the comparison. when all the enable bits are set to ?1?, alarm1 triggers once per second . note that there is no alarm byte for month and year. the alarm1 function works as a comparison between the alarm1 registers and the rtc registers. as the rtc advances, alarm1 is triggered when a match occurs between the alarm1 registers and the rtc registers. any one alarm1 register, multiple registers, or all registers can be enabled for a match. to clear alarm1, the a1f status bit must be set to ?0? with a write. table 2. interrupt control register (int) addr76543210 0eh eosc 0 0 rs2 rs1 intcn a2ie a1ie default00011000 table 3. frequency selection of f out pin frequency f out (hz) rs2 rs1 comment 32768 1 1 free-running crystal clock 8192 1 0 free-running crystal clock 4096 0 1 free-running crystal clock 1 0 0 sync at rtc write table 4. alarm interrupt selection with intcn, a2ie and a1ie bits intcn a2ie a1ie irq1 /f out irq2 000 f out high 001 f out a1f 010 f out a2f 011 f out a1f or a2f 1 0 0 high high 101 high a1f 110 a2f high 111 a2f a1f table 5. status register (sr) addr 7 6 5 4 3 2 1 0 0fh osf 0 0 0 0 0 a2f a1f default 1 0 0 0 0 0 0 0 table 6. alarm1 interrupt with enable bits selection a1dw/dt a1m1 a1m2 a1m3 a1m4 alarm1 interrupt x 1111 every second x 0111 match second x 1011 match minute isl12057
11 fn6755.1 march 3, 2011 note: ?x? is ?don?t care?; it can be set to 0 or 1. following is example of an alarm1 interrupt : a single alarm will occur on monday at 11:30 a.m. (monday is when dw = 2). set the alarm1 registers as follows: after these registers are set, an alarm is generated when the rtc advances to exactly 11:30 a.m. on january 1 (after seconds changes from 59 to 00) by setting the a1f bit in the status register to ?1?. alarm2 registers addresses [address 12h to 14h] the alarm2 register bytes are set up identically to the rtc register bytes except that the msb of each byte functions as an enable bit (enable = ?0?). these enable bits specify which alarm registers (minutes, hour, and date/day) are used to make the comparison. when all the enable bits are set to ?1?, alarm2 will trigger once per minute. note that there are no alarm bytes for seconds, month, and year. the alarm2 function works as a comparison between the alarm2 registers and the rtc registers. as the rtc advances, alarm2 is triggered when a match occurs between the alarm2 registers and the rtc registers. any one alarm2 register, multiple registers, or all registers can be enabled for a match. to clear alarm2, the a2f status bit must be set to ?0? with a write. note: ?x? is ?don?t care?; it can be set to 0 or 1. following is example of alarm2 interrupt : a single alarm will occur on the first day of every month at 20:00 military time. set the alarm2 registers as follows: after these registers are set, an alarm is generated when the rtc advances to exactly 20:00 on monday (after minutes changes from 59 to 00) by setting the a2f bit in the status register to ?1?. i 2 c serial interface the isl12057 supports a bi-directional, bus-oriented protocol. the protocol defines any device that sends data x (see note) 1101 match hour 0 1110 match date 1 1110 match day 0 0011match sec ond and minute 0 0101match sec ond and hour 0 0000match sec ond, minute and hour . . . . . . . . . . . . 0 1000match minute hour and date 0 0000match sec ond, minute hour and date . . . . . . . . . . . . 1 1000match minute, hour, and day 1 0000match sec ond, minute, hour, and day alarm1 register bit description 76543210hex a1sc 10000000 80hsec onds disabled a1mn 00110000 30hminutes set to 30, enabled a1hr 01010001 51hhours set to 11am, enabled a1dw/dt 01000010 42hday set to 1, enabled table 6. alarm1 interrupt with enable bits selection (continued) a1dw/dt a1m1 a1m2 a1m3 a1m4 alarm1 interrupt table 7. alarm2 interrupt with enable bits selection a2dw/dt a2m2 a2m3 a2m4 alarm2 interrupt x (see note) 1 1 1 every minute (second=00) x 0 1 1 match minute x 1 0 1 match hour 0 1 1 0 match date 1 110 match day x 0 0 1 match minute and hour 0 1 0 0 match hour and date 0 0 1 0 match minute and date 0 0 0 0 match minute, hour, and date 1 0 1 0 match minute and day 1 1 0 0 match hour and day 1 0 0 0 match minute, hour, and day alarm2 register bit description 76543210hex a2mn 10000000 80hminutes disabled a2hr 00100000 20hhours set to 20, enabled a2dw/dt 00000001 01hdate set to 1st, enabled isl12057
12 fn6755.1 march 3, 2011 onto the bus as a transmitter and the receiving device as the receiver. the device controlli ng the transfer is the master, and the device being controlled is the slave. the master device always initiates data transfers and provides the clock for both transmit and receive operations. therefore, the isl12057 operates as a slave device in all applications. all communication over the i 2 c interface is conducted by sending the msb of each byte of data first. protocol conventions data states on the sda line can change only during scl low periods. sda state cha nges during scl high are reserved for indicating start and stop conditions (see figure 7). on power-up of the isl12057, the sda pin is in the input mode. all i 2 c interface operations must begin with a start condition, which is a high to low transition of sda while scl is high. the isl12057 continuously monitors the sda and scl lines for the start condition and does not respond to any command until this condition is met (see figure 7). a start condition is ignored during the power-up sequence. all i 2 c interface operations must be terminated by a stop condition, which is a low to high transition of sda while scl is high (see figure 7). a stop condition at the end of a read operation or at the end of a write operation to memory only places the device in its standby mode. an acknowledge (ack) is a software convention used to indicate a successful data transfer. the transmitting device, either master or slave, releases the sda bus after transmitting 8 bits. du ring the ninth clock cycle, the receiver pulls the sda line low to acknowledge reception of the 8 bits of data (see figure 8). the isl12057 responds with an ack after recognition of a start condition followed by a valid identification byte, and once again after successful rece ipt of an address byte. the isl12057 also responds with an ack after receiving a data byte of a write operation. th e master must respond with an ack after receiving a data byte of a read operation. figure 7. valid data changes, start, and stop conditions figure 8. acknowledge response from receiver sda scl start data data stop stable change data stable sda output from transmitter sda output from receiver 8 1 9 start ack scl from master high impedance high impedance isl12057
13 fn6755.1 march 3, 2011 device addressing following a start condition, the master must output a slave address byte. the seven msbs are the device identifier. these bits are ?1101000?. slave bits ?1101? access the register. slave bits ?000? specify the device select bits. the last bit of the slave address byte defines a read or write operation to be performed. when this r/w bit is a ?1?, then a read operation is selected. a ?0? selects a write operation (see figure 10). after loading the entire slave address byte from the sda bus, the isl12057 compares the device identifier and device select bits with ?1101000?. upon a correct compare, the device outputs an acknowledge on the sda line. following the slave byte is a one-byte word address. the word address is either supplied by the master device or obtained from an internal counter. on power-up, the internal address counter is set to addr ess 0h, so a current address read of the rtc array starts at address 0h. when required, as part of a random read, the master must supply the 1 word address bytes as shown in figure 11. in a random read operation, t he slave byte in the ?dummy write? portion must match t he slave byte in the ?read? section. for a random read of the clock/control registers, the slave byte must be ?1101000x? in both places. write operation a write operation requires a star t condition, followed by a valid identification byte, a valid address byte, a data byte, and a stop condition. after each of the three bytes, the isl12057 responds with an ack. at this point, the i 2 c interface enters a standby state. read operation a read operation consists of a 3- byte instruction followed by one or more data bytes (see figure 11). the master device initiates the operation by issuing the following sequence: a start, the identification byte with the r/w bit set to ?0?, an address byte, a second start, and a second identification byte with the r/w bit set to ?1?. after each of the three bytes, the isl12057 responds with an ack. then, the isl12057 transmits data byte s, as long as the master device responds with an ack during the scl cycle following the eighth bit of each byte. the master device terminates the read operation (issuing a stop condition) following the last bit of the last data byte (see figure 11). the data bytes are from the memory location indicated by an internal pointer. this pointer?s initial value is determined by the address byte in the read operation instruction. it increments by one during transmission of each data byte. after reaching the memory location 13h, the pointer ?rolls over? to 00h, and the device continues to output data for each ack received. figure 9. sequential byte write sequence s t a r t s t o p identification byte first data byte a c k signals from the master signals from the isl12057 a c k 10 0 11 a c k write signal at sda 0000 000 address byte a c k last data byte a c k figure 10. slave address, word address, and data bytes slave address byte d7 d6 d5 d2 d4 d3 d1 d0 a0 a7 a2 a4 a3 a1 data byte a6 a5 1 10 0 1 0 r/w 0 word address isl12057
14 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6755.1 march 3, 2011 application section oscillator crys tal requirements the isl12057 uses a standard 32.768khz crystal. either through-hole or surface-mount crystals can be used. table 8 lists some recommended surface-mount crystals and the parameters of each. this list is not exhaustive, and other surface-mount devices can be used with the isl12057 if their specifications are very si milar to the devices listed. the crystal required parallel load capacitance is 6pf, and equivalent series resistance needs to be less than 50k. the crystal?s temperature range sp ecification should match the application. many crystals are rated for -10c to +60c (especially through-hole and tuning fork types), so an appropriate crystal should be selected if extended temperature range is required. layout considerations the crystal input at x1 has a very high impedance, and oscillator circuits operati ng at low frequencies (such as 32.768khz) are known to pick up noise very easily if layout precautions are not followed. most instances of erratic clocking or large accuracy errors can be traced to the susceptibility of the oscillator circuit to inte rference from adjacent high-speed clock or data lines. careful layout of the rtc circuit will avoid noise pickup and ensure accurate clocking. figure 12 shows a suggested layout for the isl12057 device using a surface-mount crystal. two main precautions should be followed: 1. do not run the serial bus lines or any high-speed logic lines in the vicinity of the crystal. these logic level lines can induce noise in the osc illator circuit to cause misclocking. 2. add a ground trace around the crystal with one end terminated at the chip ground. this will provide termination for emitted noise in the vicinity of the rtc device. in addition, it is a good idea to avoid a ground plane under the x1 and x2 pins and the crystal, as this will affect the load capacitance and therefore the oscillator accuracy of the circuit. if the irq1 /f out pin is used as a clock, it should be routed away from the rtc device as well. the trace for the v cc pins can be treated as a ground, and it should be routed around the crystal. figure 11. read sequence signals from the master signals from the slave signal at sda s t a r t identification byte with r/w = 0 address byte a c k a c k 0 s t o p a c k 1 identification byte with r/w = 1 a c k s t a r t last read data byte first read data byte a c k 10 1 1000 10 1 10 00 table 8. suggested surface mount crystals manufacturer part number citizen cm200s microcrystal ms3v ecs ecx-306 figure 12. suggested layout for isl12057 and crystal isl12057
15 fn6755.1 march 3, 2011 isl12057 package outline drawing m8.118 8 lead mini small outline plastic package rev 3, 3/10 detail "x" side view 2 typical recommended land pattern top view pin# 1 id 0.25 - 0.036 detail "x" 0.10 0.05 (4.40) (3.00) (5.80) h c 1.10 max 0.09 - 0.20 33 gauge plane 0.25 0.95 ref 0.55 0.15 b 0.08 c a-b d 3.00.05 12 8 0.85010 seating plane a 0.65 bsc 3.00.05 4.90.15 (0.40) (1.40) (0.65) d 5 5 side view 1 dimensioning and tolerancing conform to jedec mo-187-aa plastic interlead protrusions of 0.15mm max per side are not dimensions in ( ) are for reference only. dimensions are measured at datum plane "h". plastic or metal protrusions of 0.15mm max per side are not dimensions are in millimeters. 3. 4. 5. 6. notes: 1. 2. and amsey14.5m-1994. included. included. 0.10 c m
16 fn6755.1 march 3, 2011 isl12057 package outline drawing l8.2x2 8 lead ultra thin dual flat no-lead col plastic package (utdfn col) rev 3, 11/07 typical recommended land pattern detail "x" top view bottom view side view located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 id entifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: 2.00 7x 0.4 0.1 0.15 ( 1 . 8 ) (4x) ( 8x 0 . 25 ) ( 1x 0 .70 ) ( 6x 0 . 5 ) 0 . 55 max base plane c seating plane 0.08 c 0.10 c 0.25 +0.05 / -0.07 see detail "x" 0.10 4 ca mb index area 6 pin 1 2.00 a b pin #1 index area 0.50 2x 1.5 6x 6 ( 7x 0 . 60 ) 0 . 00 min. 0 . 05 max. c 0 . 2 ref 5 4 8 1 1x 0.5 0.1
17 fn6755.1 march 3, 2011 isl12057 package outline drawing m8.15 8 lead narrow body small outline plastic package rev 2, 11/10 detail "a" top view index area 123 -c- seating plane x 45 notes: 1. dimensioning and tolerancing per ansi y14.5m-1982. 2. package length does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 3. package width does not include interlead flash or protrusions. interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 4. the chamfer on the body is optional. if it is not present, a visual index fea- ture must be located with in the crosshatched area. 5. terminal numbers are shown for reference only. 6. the lead width as measured 0.36mm (0.014 inch) or greater above the seat- ing plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 7. controlling dimension: millimeter. co nverted inch dimensions are not necessarily exact. 8. this outline conforms to jedec publication ms-012-aa issue c. side view ?a side view ?b? 1.27 (0.050) 6.20 (0.244) 5.80 (0.228) 4.00 (0.157) 3.80 (0.150) 0.50 (0.20) 0.25 (0.01) 5.00 (0.197) 4.80 (0.189) 1.75 (0.069) 1.35 (0.053) 0.25(0.010) 0.10(0.004) 0.51(0.020) 0.33(0.013) 8 0 0.25 (0.010) 0.19 (0.008) 1.27 (0.050) 0.40 (0.016) 1.27 (0.050) 0.200 1 2 3 4 5 6 7 8 typical recommended land pattern 2.41 (0.095) 0.76 (0.030)

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